The invention lies in the memory technology field and is particularly suitable for dynamic RAM memories (DRAMs). DRAM technology, however, is not the exclusive field of application of the invention.
The invention relates to a circuit configuration for reading and writing binary information at a memory cell field forming a matrix-type arrangement of rows and columns of memory cells. Access to any memory cell is accomplished by the excitation of a word line which is allocated to the relevant row and the actuation of a bit line which is allocated to the relevant column. This driving is effected by a selectively allocated write/read circuit. Each write/read circuit contains a latch flipflop with at least one data terminal which is connected on one side to an allocated bit line and on the other side, by way of a gate circuit that is controllable by means of a column selection signal, to a data line.
In conventional memory matrices, access to any memory cell is accomplished by the excitation of a word line that is allocated to the relevant row and the actuation of a bit line that is allocated to the relevant column. The latter is accomplished by means of write/read circuits which transfer information bits from a message source to the bit lines in the write operation and from the bit lines to a message sink in the read operation. Since the charge states of the memory cells which describe the binary values 0 (zero) and 1 (one) of the stored information differ only by a small level difference, the write/read circuits must be designed to effectuate an amplification in the read operation, and for this reason these circuits are herein also referred to as xe2x80x9cread amplifiers,xe2x80x9d as they are commonly known, even though they are also used in the write operation.
The standard read amplifiers in use today are built as what are known as latch flipflops, i.e. as transistorized bistable flipflops that are switchable between two defined extreme states representing the binary values 0 and 1. Each of these opposing states can be triggered by the build-up of a triggering voltage of one or the other polarity at a data terminal, whereby the circuit is driven in a self-perpetuating extreme state in which the data terminal is drawn to (or close to) one or the other potential of the supply voltage. The data terminal is thus locked at a binary value indicated by the polarity of the triggering voltage (the binary value is xe2x80x9clatchedxe2x80x9d), and the relevant item of binary data can be handed over with sufficient power and endurance.
Customarily, the data terminal of the latch flipflop contained in the read amplifier is connected on one side to an allocated bit line and on the other side, by way of a gate circuit that can be controlled by a column selection signal, to the data line leading to the message source or message sink. In the case of paired differential bit lines where each bit line path forms a differential pair of two bit lines, and the data line path likewise forms a differential pair of two data lines, the latch flipflops are provided with two data terminals, as in the case of a differential amplifier, each of these terminals being connected on one side to an allocated instance of the bit lines forming the relevant pair and on the other side, by way of a respectively allocated gate circuit half, to an allocated instance of the two data lines.
For reading and writing at a memory cell, after the relevant word line is generated, at least the read amplifier which is responsible for the relevant column is activated, so that current for building up the trigger voltage flows at the data terminal of the latch flipflop by way of the relevant bit line in dependence upon the charge status of the cell, whereupon the flipflop assumes the binary state representing the information content of the cell. The potential of the data terminal is thereby drawn to the level indicating the information. The column selection signal is then applied in order to connect the data terminal to the data line by way of the gate circuit. In the read operation, the potential of the data terminal is taken over by the data line. In the write operation, the data line is impressed by the level for the write information from the outside, which naturally flips the latch flipflop by way of the data terminal if the binary state of the flipflop hitherto does not correspond to the write information (i.e. if the cell content must be modified).
The response sensitivity of the read amplifier in the read operation, i.e. its voltage/current amplification (transconductance), depends on the amplification of the transistors contained in the latch flipflop. The higher this amplification is, the faster and more reliably the latch flipflop can be flipped by the small current delivered by a selected memory cell from its unlatched initial state into one of the two stable binary states and latched in this state. Engineers therefore strive to construct the read amplifier optimally strong in order to achieve high read speeds. But it may turn out that the writing of the information from the data line path into the cell field is difficult or impossible. This is rooted in the abovementioned fact that in the write operation the latch flipflop may have to be flipped into another state, i.e. the read amplifier may have to be xe2x80x9crewrittenxe2x80x9d. But when this is dimensioned for power, it becomes difficult or time-consuming to flip the latch flipflop from one assumed binary state into the other, especially since the gate circuit by way of which the write information runs from the data line into the latch flipflop limits current.
Hitherto, this problem, which is particularly severe in ultra-high-speed DRAMs, has been solved by dimensioning the write drivers that generate the write levels for ultra-high power. But when the read amplifiers are designed for greater and greater power, this technique becomes less and less expedient, since the drivers become ever larger and slower and consume ever greater amounts of current.
Another solution would be to utilize a separate write circuit in the read amplifier. But this would entail a substantial space outlay.
U.S. Pat. No. 4,435,793 describes a circuit configuration for reading binary information from a memory cell field containing a write/read circuit with a latch flipflop having a switching device for activating/deactivating the flipflop and an additional in-series switching device which is actuated by a column decoder.
The object of the present invention is to provide a circuit configuration for reading and writing binary information from and to a memory cell matrix which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which renders possible a perfect writing of information at a memory cell field given low circuitry and energy outlays and regardless of the read amplification.
With the above and other objects in view there is provided, in accordance with the invention, a circuit configuration for reading and writing binary information at a memory cell field arranged in a matrix of rows and columns of memory cells each connected to a word line allocated to a row and a bit line allocated to a column of the memory cells, comprising:
write/read circuits each connected to access a respective memory cell via a word line and a bit line;
each of the write/read circuits containing a gate circuit controllable by a column selection signal, and a latch flipflop having a current supply and at least one data terminal connected between an allocated bit line and a data line via the gate circuit;
a switching device connected to the current supply of the latch flipflops, the switching device, subsequently to an excitation of any word line, interrupting the current supply to the latch flipflops in the write/read circuits that are controllable by a column selection signal, from an instant no earlier than a time at which the respective latch flipflop assumes a state indicating an information content of the accessed memory cell and, at the latest, within an active interval of the relevant column selection signal.
In other words, the invention is based on a circuit configuration for reading and writing binary information at a memory cell field forming a matrix of rows and columns of memory cells. Access to any memory cell is accomplished by the excitation of a word line that is allocated to the relevant row and the actuation of a bit line that is allocated to the relevant column by means of respectively allocated write/read circuits. Each write/read circuit contains a latch flipflop having at least one data terminal which is connected on one side to an allocated bit line and on the other side, by way of a gate circuit that is controllable by a column selection signal, to a data line. The invention provides a switching device which, subsequent to the excitation of any word line, interrupts the current supply to the latch flipflop in the write/read circuits which are actuated by a column selection signal, from an instant which is no earlier than when the relevant latch flipflop assumes the state indicating the information content of the accessed memory cell and which, at the latest, falls within the active interval of the relevant column selection signal.
The invention thus contains a rather simple circuit measure which merely provides for a cutoff of the current supply to the latch flipflops that are to be selected for an access operation at a suitable instant after the latch flipflop has set itself to the binary state which is determined by the cell contents and before a write operation could potentially set in. This disconnection prevents the write process from having to fight the read amplification; the effort in the write operation is thus independent of the read amplification.
In accordance with an added feature of the invention, the switching device includes a switch in each of the write/read circuits, the cut-out switch interrupting a connection between a supply potential and the relevant latch flipflop. The inventively provided switching device advantageously contains a cut-out switch in each read/write circuit, which is provided for interrupting the connection between a supply potential and the relevant latch flipflop. Its realization requires only one additional element, for instance a field-effect transistor (FET), per bit line (that is to say per bit line pair in the event of paired bit lines). No other circuits are needed in the region of the write/read circuit, so that the space outlay is minimal. Given a suitable design of the cut-out switch, the column selection signal of the relevant write/read circuit can be used directly for its actuation, in order to initiate the interruption of the current supply at the beginning of this column selection signal and to maintain it for the duration of the column selection signal. The advantage of this is that no additional lines must be led into the write/read circuit.
In accordance with an additional feature of the invention, each switch responds to the column selection signal of the relevant write/read circuit so as to initiate the interruption of the current supply at a beginning of the column selection signal and to maintain the interruption for the duration of the column selection signal.
In accordance with another feature of the invention, each latch flipflop includes a first transistor pair with each transistor of the first transistor pair having a control electrode connected to a main electrode of the respective other transistor of the first transistor pair, one of the transistors of the transistor pair has a control electrode connected to a data terminal of the latch flipflop, and the other main electrodes of the two transistors are connected to a connection node for receiving a first supply potential, and wherein the switch is disposed between the connection node and a supply terminal carrying the first supply potential of the respective write/read circuit.
In accordance with a further feature of the invention, each of the data lines is shared by a plurality of the write/read circuits, and a latch circuit is connected to each data line, the latch circuit locks a binary state of the data terminal of a latch flipflop coupled onto the data line by the allocated gate circuit at the respective data line.
In accordance with a concomitant feature of the invention, the latch circuit comprises a transistor pair corresponding to the first transistor pair with respect to conductivity type and in which the control electrode of each transistor is connected to a main electrode of the respective other transistor, the control electrode of one of the transistors is connected to the shared data line, and the other main electrodes of the two transistors are connected to a supply terminal carrying the first supply potential.
In these specific developments of the invention, it can thus be ensured by additional latching circuit parts at the data line that no information is lost, even given relatively long interruptions of the current supply of the latch flipflop, such as occur when long column selection impulses are utilized. Yet, given the utilization of data lines which are each shared by a plurality of write/read circuits, these circuit parts are required at the periphery only once per data line.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for reading and writing information at a memory cell field, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.